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product structu re silicon monolithic integrated circuit this product is not designed protection against radioactive ray s 1/ 26 tsz22111 ? 14 ? 001 ? 2012 rohm co., ltd. all rights reserved. tsz02201-0r2r0g100420-1-2 17.aug.2015 rev.002 www.rohm.com serial eeprom series standard eeprom plug & play eeprom BU9883FV-W general description BU9883FV-W is for ddc 3 ports, 2k x 8 bit array 3 bank eeprom. features there are 3 banks, 1 bank compose of 256 word address x 8 bit eeprom there are 3 ddc interface channels, and each channel can access each bank independently from other ports. 2k bit x 3 bank memory bits can be accessed from write port (port0). operate voltage (3.0v to 5.5v) built in diode for power supply from hdmi ports and system. automatic erase 8 byte page write mode low power consumption ? at write action ( 5.0v ) : 1.2ma (typ.) ? at read action (5.0v) : 0.2ma(typ.) 1port action ? at standby action ( 5.0v ) : 50 a(typ .) data security write protect pin can switch write port inhibit to write at low v cc endurance : 1,000,000 erase/write cycles data retention 40 years filtered inputs in all scl ? sda for noise suppression shipment data all address ffh package w(typ.) x d(typ.) x h(max.) typical application circuit ssop-b16 5.00mm x 6.40mm x 1.35mm rohm BU9883FV-W hdmi switch 47k pwr_hdmi1 vcc0 wpb scl0 sda0 gnd sda3 scl3 sda2 scl2 sda1 scl1 scl_sink sda_sink ddc_scl1 ddc_sda1 47k pwr_hdmi2 ddc_scl2 ddc_sda2 47k pwr_hdmi3 ddc_scl3 ddc_sda3 vcc1 sda1 scl1 vcc2 sda2 scl2 vcc3 sda3 scl3 0.1uf 0.1uf 0.1uf hdmi re ceiver ddc_sda ddc_scl 0.1uf pwr_sys hdmi sink 47k 47k 47k controller wpb_out i 2 c_scl i 2 c_sda 0.1uf vcc out datashee t downloaded from: http:///
2/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 absolute maximum ratings (ta=25 ) parameter symbol rating unit remarks supply voltage v cc -0.3 to 6 .5 v power dissipation pd 0.4 w degradation is done at 3.0mw/ for operation above 25 storage temperature tstg -65 to 125 operating temperature t opr -40 to 85 terminal voltage - -0.3 to v cc 0.3 v the max value of terminal voltage is not over 6.5v memory cell characteristics (ta=25 , v cc 0 to 3 = 3.0v to 5.5 v) *1:not 100 tested recommended operating ratings parameter symbol rating unit supply voltage v cc 3.0 to 5.5 v input voltage v in 0 to v cc 0 to 3 input/output capacity (ta=25 , frequency=5mhz) parameter symbol min. typ. max. unit sda pins (sda0,1,2,3) *1 c in - 7 - pf scl pins (scl0,1,2,3) *1 c in2 - 7 - pf *1:not 100 tested electrical characteristics - dc operating (unless otherwise specified, ta=- 40 to 85 , v cc 0 to 3 = 3.0v to 5.5v) parameter symbol specification unit test condition min. typ. max. "h" input voltage0 vih0 0.7 x v cc 0 - v cc 0+0.5 v 3.0 v cc 0 5.5v(scl0, sda0) "l" input voltage0 vi l0 -0.3 - 0.3 x v cc 0 v 3.0 v cc 0 5.5v(scl0, sda0) "h" input voltage1 vih1 0.7 x v cc 1 - v cc 1+0.5 v 3.0 v cc 1 5.5v(scl1, sda1) "l" input voltage1 vil1 -0.3 - 0.3 x v cc 1 v 3.0 v cc 1 5.5v(scl1, sda1) "h " input voltage2 vih2 0.7 x v cc 2 - v cc 2+0.5 v 3.0 v cc 2 5.5v(scl2, sda2) "l" in put voltage2 vil2 -0.3 - 0.3 x v cc 2 v 3.0 v cc 2 5.5v(scl2, sda2) "h" in put voltage3 vih3 0.7 x v cc 3 - v cc 3+ 0 .5 v 3.0 v cc 3 5.5v(scl3, sda3) "h " in put voltage3 vil3 -0.3 - 0.3 x v cc 3 v 3.0 v cc 3 5.5v(scl3, sda3) "l " output voltage0 vol0 - - 0. 4 v iol=3.0ma , 3.0v v cc 0 5.5v(sda0) "l " output voltage1 vol1 - - 0.4 v io l=3.0ma , 3.0v v cc 1 5.5v(sda1) "l " output voltage2 vol2 - - 0.4 v io l=3.0ma , 3.0v v cc 2 5.5v(sda2) "l " output voltage3 vol3 - - 0.4 v io l=3.0ma , 3.0v v cc 3 5.5v(sda3) wp "h " in put voltage vih4 0.7 x v cc 0 - v cc 0+0.3 v 3.0 v cc 0 5.5v(wpb) wp "l " in put voltage vil4 -0.3 - 0.3 x v cc v 3.0 v cc 0 5.5v(wpb) input leakage current0 il i0 -1 - 1 a vin=0 to 5.5v(scl0 to 3) in put leakage current1 il i1 55 110 230 a wpb=5.5v , v cc =5.5v output leakage current0 ilo0 -1 - 1 a vout=0 to 5.5(sda0 to 3) operating current icc1 - - 2.0 ma v cc 0=5.5v, fscl=400khz twr=5ms byte write, page write i cc2 - - 1.0 ma v cc 0 to 3=5.5v, fscl=400khz random read, current read,sequential read, (each port operation) standby current i sb 0 - - 100 a v cc 0=5.5v, sda0 to 3=scl0 to 3=5.5v, wp b=gnd standby current isb1 - - 100 a v cc 1=5.5v, sda0 to 3=scl0 to 3=5.5v, wp b=gnd standby current isb2 - - 100 a v cc 2=5.5v, sda0 to 3=scl0 to 3=5.5v, wp b=gnd standby current isb3 - - 100 a v cc 3=5.5v, sda0 to 3=scl0 to 3=5.5v, wp b=gnd parameter specification unit min. typ. max. write/erase cycle *1 1,000,000 - - cycles data retention *1 40 - - years downloaded from: http:///
3/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 electrical characteristics -ac operating (ta=- 40 to 85 , v cc 0 to 3 = 3.0v to 5.5v) parameter symbol 3.0 v cc 0 to 3 5.5v unit min. typ. max. clock frequency f scl - - 400 khz data clock high period t high 0.6 - - s data clock low period t lo w 1.2 - - s sda0 to 3 and scl0 to 3 rise time *1 t r - - 0.3 s sda0 to 3 and scl0 to 3 fall time *1 t f - - 0.3 s start condition hold time t hd:sta 0.6 - - s start condition setup time t su:sta 0.6 - - s input data hold time t hd : dat 0 - - ns input data setup time t su:dat 100 - - ns output data delay time t pd 0.1 - 0.9 s output data hold time t dh 0.1 - - s stop condition setup time t su:sto 0.6 - - s bus free time t buf 1.2 - - s write cycle time t wr - - 5 ms noise spike width (sda0 to 3 and scl0 to 3) ti - - 0.1 s wp hold time t hd:wp 0 - - ns wp setup time t su:wp 0.1 - - s wp valid time t high:wp 1.0 - - s *1 : not 100% teseted sync data input / output timing sda data is latched into the chip at the rising edge of the scl clock. (this i s commonness in all port.) output date toggles at the falling edge of the scl clock. (this is commonness in all port.) figure 1. synchronous data timing sda (in) scl sda (out) t hd :sta t hd :dat t su :dat t buf t pd t dh t low t high t r t f sda scl t su :sta t su :sto t hd :sta start bit stop bit downloaded from: http:///
4/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 block diagram pin configuration pin descriptions pin no. pin name i/o functions 1 v cc 1 - power supply 2 scl1 input serial clock input 3 sda1 input /output slave and word address, serial data input serial data output 4 wpb input write protect terminal(1 : write enable, 0 : write disable) 5 v cc out - terminal of diode. connect bypass capacitor. 6 sda0 input /output slave and word address, serial data input serial data output 7 scl0 input serial clock input 8 v cc 0 - power supply 9 v cc 3 - power supply 10 scl3 input serial clock input 11 sda3 input /output slave and word address, serial data input serial data output 12 gnd - reference voltage of all input / output 13 n.c - none connect terminal. don t connect each other. 14 sda2 input /output slave and word address, serial data input serial data output 15 scl2 input serial clock input 16 v cc 2 - power supply vcc1 scl1 sda1 wpb v cc out sda0 scl0 vcc0 7 6 5 4 3 2 1 10 11 12 13 14 15 16 BU9883FV-W 8 9 vcc2 scl2 sda2 n.c gnd sda3 scl3 vcc3 top view low voltage logic vcc1 vcc2 vcc3 vcc0 rd rd wr port 0 rd wr wr rd port 1 port 2 port 3 sda0 scl0 voltage detect logic wpb v cc out en i/o (port1) level shifter bank0 (2kbit eeprom) rd en i/o (port2) level shifter bank1 (2kbit eeprom) rd en i/o (port3) level shifter bank2 (2kbit eeprom) control control control level shifter con trol en scl0 sda0 i/o (port0) l do scl1 sda1 scl2 scl3 sda2 sda3 downloaded from: http:///
5/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 figure 3. h input voltage1 v ih1 (scl1,sda1) typical performance curves (the following values are typ. ones.) figure 5. h input voltage3 v ih3 (scl3,sda3) figure 2. h input voltage0 v ih0 (scl0,sda0) figure 4. h input vo ltage2 v ih2 (scl2,sda2) downloaded from: http:///
6/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 typical performance curves C continued figure 9. l input voltage3 v il3 (scl3,sda3) figure 7. l input voltage1 v il1 (scl1,sda1) figure 8. l input voltage2 v il2 (scl2,sda2) figure 6. l input voltage0 v il0 (scl0,sda0) downloaded from: http:///
7/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 typical performance curves C co ntinued figure 13. l output voltage3 v 0l3 -i 0l (vcc3=3.0v) (sda3) figure 11. l output voltage1 v 0l1 -i 0l (vcc1=3.0v) (sda1) figure 12. l output voltage2 v 0l2 -i 0l (vcc2=3.0v) (sda2) figure 10. l output voltage0 v 0l0 -i 0l (vcc0=3.0v) downloaded from: http:///
8/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 typical performance curves C continued figure 17. input leak current1 i li1 (wpb) figure 15. wp l input voltage v il4 figure 16. input leak current0 i u0 (scl0 to 3) figure 14. wp h input voltage v ih4 downloaded from: http:///
9/ 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 typical performance curves C continued figure 21. standby current0 i sb0 figure 19. current consumption at reading i cc1 figure 20. current consumption at reading i cc2 figure 18. output leak current0 i l o0 (sda0 to 3) downloaded from: http:///
10 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 typical performance curves C continued figure 25. clock frequency f scl figure 23. standby current2 i sb2 figure 24. standby current3 i sb3 figure 22. standby current1 i sb1 downloaded from: http:///
11 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 typical performance curves C continued figure 29. start condition setup time t su:sta figure 27. data clock low period t low figure 28. start condition hold time t hd:sta figure 26. data clock high period t high downloaded from: http:///
12 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 typical performance curves C continued figure 33. stop condition setup time t su:sto figure 31. input data setup time t su :dat figure 32. output data delay time t pd figure 30. input data hold time t hd:dat downloaded from: http:///
13 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 figure 35. noise spike width t i (sda0 to 3 and scl0 to 3) typical performance curves C continued figure 34. write cycle time t wr figure 36. wp setup time t su:wp downloaded from: http:///
14 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 write cycle timing write operation bu9883 fv -w has 2k bit eeprom in each port, there are three banks, 6k bit eeprom in this d evice. each bank eeprom can be written through port0. there is no write operation through port1,2,3. when this device is accessed throgh port0, wpb terminal must be s et to high. (see to table 1) re ad operation each bank eeprom can be read through each port. the relation ship of access port and access bank is describe table 2. table 1 table 2 port0 bank1 to 3 port0 bank1 to 3 port1 no write operation port1 bank1 port2 no write operation port2 bank2 port3 no write operation port3 bank3 when eeprom access through port0, p1, p0 bits in slave address appoint access bank.(refer to table 3) table 3 p1 p0 p1,p0 bit and access bank 0 0 no bank selected 0 1 bank1 1 0 bank2 1 1 bank3 note) when p1 =0, p0=0 : this device doesnt return ac knowlege. during port0 access, wpb terminal must be set to high, then port1 to 3 accesses will be cancelled. in accessing from port1 to 3, set wpb termianl to low device operation start condition ? all commands are proceeded by the start condition, which is a high to low transition of sda0 to 3 when scl0 to 3 is high. ? this device continuously monitors the sda0 to 3 and scl0 to 3 lines for the start condition and will not respond to any command until this condition has been met. (refer to figure 1) stop condition ? all communications must be terminated by a stop condition, which i s a low to high transition of sda0 to 3 when scl0 to 3 is high. (refer to figure 1) the stop condition initiates inte rnal write cycle to write the data into memory array af ter write sequence. the stop condition is also used to place the device into the standby power mode after read sequ ence. a stop condition can only be issued after the transmitting devi ce has released the bus. notice on write command ? in write command, af ter transmit write data, if there are no stop condition, eeprom data dont change. sda0 scl0 d0 ack stop condition start condition t wr write data(n) figure 37. wr ite cycle timing downloaded from: http:///
15 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 device addressing ? following a start condition, the master output the device addres s of the slave to be accessed. ? the most significant four bits of the slave address are the device type indentifier, for t his device, this is fixed as 1010. ? the next three bit specify a particular device. for port0 access, tha t are set 0, p1, p0, for port 1 to 3 access, that must be set 000. ? the last bit of the stream determines the operation to be performed. when set to 1 a read o peration is selected ; when set to 0, a write operation is selected. r/w set to 0 ? ? ? ? ? ? ? ? write r/w set to 1 ? ? ? ? ? ? ? ? read acknowledge ? acknowledge is a software convention used to indicate successful data transfers.the master or the slave will release the bus after transmitting eight bits.during the ninth clock cy cle, the receiver will pull the sda line low to acknowled gethat the eight bits of data has been received. ? this device will respond with an acknowledge after recogn ition of a start condition and its slave address.if both the device and a write operation have been selected, this de vice will respond with an acknowledge, after the receipt o f each subsequent 8-bit word. ? in the read mode, this device will transmit eight bit of data , release the sda line, and monitor the line for an acknowledge. ? if an acknowledge is detected, and no stop condition is generat ed by the master, this device will continue to transmit the data. ? if an acknowledge is not detected, this device will terminate fu rther dat a transmissions and await a stop condition before returning to the standby mode. ? this device dosen't return acknouwedge in internal write cycle. port0 access commands for port0 access, wpb terminal must be set to high. this write commands operate eeprom write sequence at address which i s appointed by p1, p0. when the master generates a stop condition, this device begins the internal write cycle to the nonvolatile array. figure 38. acknowledge response from receiver figure 39. byte write cycle timing (port0) p1 0 wa7 1 1 0 0 w r i t e s t a r t r / w 1st word address(n) sda line slave address wa0 a c k d7 data(n) d0 a c k s t o p p0 wpb sda scl 1 8 9 acknowledge signal (ack signal) start condition (start bit) from - com ic output data sda - com output data) downloaded from: http:///
16 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 this device is capable of eight byte page write operation. after the receipt of each word, the three low order address bits are internally incremented by one. the most significant address bits (wa7 to wa3) remain constant, if the maste r transmits more than 8 words. the relationship of p1, p0 inputs and access bank is described as fol lows. p1 p0 bank 0 0 no opearation 0 1 bank1 1 0 bank2 1 1 bank3 don't set p1, p0=0, 0. if p1, p0 are set to 0, there is no target bank, so t his device doesn't return acknowledge. wpb terminal must be set to high during byte write cycle, an d page write cycle, and internal write cycles. if wpb is set to low in above condition, programing doesn't work, a nd during internal write cycle, wpb terminal set to low, this device terminate programing, and the data in programing ad dress is not stored correctly. random read operation allows the master to access any mem ory location which is appointed by p1, p0 bit. this operation involves a two-step process. first, the master issue a write com mand which includes the start condition and the slave address field (with r/w set to 0) followed by the address of the word b e read. this procedure sets the internal address counter of this dev ice to the desired address. after the word address acknowledge is received by the master, the master immediate ly reissues a start condition followed by the slave address field with r/w the set to 1. this device will respond with an acknowledge and then transmit the 8-data bits stored a t the addressed location. if the master does not acknowledge the transmission but does g enerate the stop condition, at this point this device discontinues transmission. figure 41. random read cycle timing port0 figure 42. current read cycle timing (port0) figure 40. page write cycle timing (port0) p1 0 wa7 1 1 0 0 w r i t e s t a r t r / w 1st word address(n) sda line slave address p0 wa0 a c k a c k p1 0 1 1 0 0 r e a d s t a r t r / w slave address p0 a c k d7 data(n) d0 a c k s t o p wpb p1 0 wa7 1 1 0 0 w r i t e s t a r t r / w 1st word address(n) sda line slave addr ess wa0 a c k a c k a c k d0 a c k s t o p wpb d7 data(n) d0 data(n+7) p0 0 1 1 0 0 sda line slave address d7 data d0 p0 p1 wpb r e a d s t o p s t ar t r / w a c k a c k downloaded from: http:///
17 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 when the command just before current read cycle is random read c ycle or current read cycle (each including sequential read cycle), data of incremented last read address (n) -th address, i.e.n, data of the (n+1)-th address is output. when the command just before current read cycle is byte write or page w rite, data of latest write address is output. current read operation allows the master to access data word sto red in internal address counter which is appointed by p1, p0 bit. this operation involves a two-step process. this device will respond with an acknowledge and then transmi t the 8-data bits stored at the addressed location. if the master does not acknowledge the transmission but doe s generate the stop condition, at this point this device discontinues transmission. note)if the master send acknowredge at after d0 output, seq uential read is selected, and this device output next address dat a, and master can't send stop condition, so master can't discontinues transmission. to stop read command, the master must send no acknowledge at aft er d0 output, and issue stop condition. during the sequential read operation, the internal address c ounter of this device automatically increments with each acknowledge received ensuring the data from address will be fol lowed with the data from n+1. for read operations, all bits of the address counter are incremented allowing the entire a rray to be read during a single operation. when the counter reaches the top of the array, it will roll over to the bottom of the array of bank and continue to transmit the data. the sequential read operation can be performed with both current read and random read. port1,2,3 access commands if the master access send commands by port1,2,3, wpb pin must be l . random read operation allows the master to access any memo ry location of the bank which is appointed by p1, p0. this operation involves a two-step process. first, the master issues a write command which includes the start condition and the slave address field (with r/w set to 0) followed by the address of the word be read. this procedure sets the internal address counter of this device t o the desired address. after the word address acknowledge is received by the master , the master immediately reissues a start condition followe d by the slave address field with r/w the set to 1. this device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. if the master does not acknowledge the transmission but does gen erate the stop condition, at this point this device discontinues transmission. st o p p1 0 d7 1 1 0 0 data(n) sda lin slave address p0 d0 d0 data(n +x d7 wpb r e a d s t a r t figure 43. sequential read cycle timing port0 figure 44. random read cycle timing port1 to 3 0 0 wa7 1 1 0 0 w r i t e s t a r t r / w 1st word address(n) sda line slave address 0 wa0 a c k a c k 0 0 1 1 0 0 r e a d s t a r t r / w slave address 0 a c k d7 data(n) d0 a c k s t o p wpb figure 45. current read cycle timing port1 to 3 0 1 1 0 0 r e a d s t a r t r / w sda line slave address a c k d7 data d0 a c k s t o p 0 0 wpb downloaded from: http:///
18 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 when the command just before current read cycle is random read cycle or current read cycle (each including sequential read cycle), data of incremented last read address (n)-th ad dress, i.e.n, data of the (n+1)-th address is output. when the command just before current read cycle is byte write or page w rite, data of latest write address is output. random read operation allows the master to access any memory location. the bank which is appointed by p1, p0. this operation involves a two-step process. first, the master issues a write command which includes the start condition and the slave address field (with r/w se t to 0) followed by the address of the word be read. this procedu re sets the internal address counter of this device to the desired address. after the word address acknowledge is receiv ed by the master, the master immediately reissues a start condition followed by the slave address field with r/w the set to 1. this device will respond with an acknowl edge and then transmit the 8-data bits stored at the addressed locati on. if the master does not acknowledge the transmission but does generate the stop condition, at this point this device discontinues transmission. note)if the master send acknowredge at after d0 output, se quential read is selected, and this device output next address data, and ma ster can't send stop condition, so master can't discontinues transmission. to stop read co mmand, the master must send no acknowledge at after d0 outpu t, and issue stop condition. during the sequential read operation, the internal address c ounter of this device automatically increments with each acknowledge received ensuring the data from address n will be followed with the data from n+1. for read operations , all bits of the address counter are incremented allowing the e ntire array to be read during a single operation. when the counter reaches the top of the array, it will roll over to the bottom of th e array and continue to transmit the data. the sequential read operation can be performed with both current read and random read. access control of port0,1,2,3 wpb terminal controls access enable of each port, as follows . port wpb terminal inputs 0 1 port0 not accessible read/write port1 read not accessible port2 read no t accessible port3 read not accessible table4 wpb terminal and port accesibility when wpb terminal is high , port0 only can access this device. in this case, when commands from port1, 2, 3 are inputted, these po rts don't return acknowledge. when wpb terminal is low, port0 access is not valid, but port1, 2, 3 can access this device this device. commands from port1, 2, 3 is performs independently other port. figure 46. sequential read cycle timing port1 to 3 0 0 d7 1 1 0 0 r e a d s t a r t r / w data(n) sda li ne slave address 0 d0 a c k a c k a c k d0 a c k s t o p data(n +x ) d7 1 wpb downloaded from: http:///
19 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 software reset software reset is executed when to avoid malfunction after pow er on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the fi gure below. (refer to figure 47 -(a), figure 47 -(b), and figure 47 - (c).) in dummy clock input area, release the sda0 to 3 buses ('h' by pull up). in dummy clock area, ack output an d read data '0' (both 'l' level) may be output from eeprom, therefore, i f 'h' is input forcibly, output may conflict and over curren t may flow, leading to instantaneous power failure of system po wer source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignore d, therefore ack is not sent back. during internal automatic write execution after write cycle input, next command (slave address) i s sent, and if the first ack signal sends back 'l', then it means end of write action, while if it sends back 'h', it means now in writing. by use of acknowledge polling, n ext command can be executed without waiting for twr = 5ms. when to write continuously, r/w = 0, when to carry out current read cycle after write, slave address r/w = 1 is sent, and if ack signal sends back 'l', then execute word address input and da ta output and so forth. 1 2 13 14 scl0 to 3 dummy clock14 start2 figure 47-(a) the case of dummy clock +start+start+ command input *start command from start input. 2 1 8 9 dummy clock9 start figure 47-(b) the case of start +9 dummy clocks +start+ command in put start normal command normal command normal command normal command start9 sda0 to 3 1 2 3 8 9 7 figure 47-(c) start9+ command input normal command normal command scl0 to 3 sda0 to 3 scl0 to 3 sda0 to 3 slave address w ord address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack=low is sent back, so input next word address and data in succession. t wr t wr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l figure 48. case to continuously write by acknowledge polling downloaded from: http:///
20 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 command cancel by start condition and stop condition during command input, by continuously inputting start condition an d stop condition, command can be cancelled. (refer to figure 49 .) however, in ack output area and during data read, sda0 to 3 buses may output 'l', and in this case, start condition an d stop condition cannot be input, so reset is not availabl e. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read c ycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. when to carry out read cycle in accession, carry out random read cycle. i/o peripheral circuit pull up resistance of sda0 to 3 terminal sda0 to 3 is nmos open drain, so requires pull up resistance . as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol 0 to 3-i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the consumption current at action. maximum value of r pu the maximum value of r pu is determined by the following factors. the following v cc , sda, r pu and i l correspond to them of each port. (1)sda0 to 3 rise time to be determined by the capacitance (cbus) o f bus line of r pu and sda0 to 3 should be tr or below. and ac timing should be satisfied even when sda0 to 3 rise time is lat e. (2)the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda0 to 3 bus and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin 0.2v cc . minimum value of r pu the minimum value of r pu is determined by the following factors. the following v cc , v ol , i ol , and r pu correspond to them of each port. (1)when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. (2)v olmax =0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1v cc . v ol max v il - 0.1 v cc ex. ) when v cc =3v, v ol =0.4v, i ol =3ma, microcontroller, eeprom v il =0.3v cc from (1) therefore, the condition (2) is satisfied. pull up resistance of scl0 to 3 terminal when scl0 to 3 control is made at cmos output port, there is no n eed, but in the case there is timing where scl0 to 3 becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k to several ten k is recommended in consideration of drive performance of output port of microcontroller. figure 49. case of cancel by start, stop condition during slave a ddress input scl0 to 3 sda0 to 3 1 1 0 0 start condition stop condition r pu 867 [ ] and v ol = 0.4 [v] v il = 0.3 3 = 0.9 [v] r pu ex. ) when v cc =3v , i l = 10 a , v ih =0.7 v cc , from (2) 0.8 3 0.7 3 10 10 -6 r pu 300 [k ] 0.8vcc v ih i l vcc - i l r pu 0.2vcc v ih 3 0.4 3 10 -3 microcontroller fig ure 50. i/o circuit diagram bus line capacity cbus r pu a BU9883FV-W sda terminal il il vcc v ol i ol v cc v ol r pu i ol r pu downloaded from: http:///
21 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 cautions on microcontroller connection rs in i2c bus, it is recommended that sda port is of open drain input/ou tput. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs between the pull up resistance rpu and the sda terminal of eeprom. this is controls over current that occurs when pmos of th e microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sda terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. the follo wing scl sda r pu and r s correspond to them of each port. maximum value of rs the maximum value of rs is determined by the following re lations. the following v cc , v ol , r s , r pu , i ol , and sda correspond to them of each port. (1)sda rise time to be determined by the capacity (cbus) of bus line of rpu an d sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by rpu and rs the moment when eep rom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1v cc . minimum value of rs the minimum value of rs is determined by over current at bu s collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source lin e in set and so forth. set the over current to eeprom 10ma or belo w. the following v cc , r pu , r s , and i correspond to them of each port. microcontroller eeprom 'l' output r s r pu 'h' output over current f ig ure 53. i/o circuit diagram figure 54. i/o circuit diagram v cc r s v cc i 1010 -3 i r s 300 example when v cc =3v, i=10ma r s 3 example when v cc =3v, v il =0.3v cc, v ol =0.4v, r pu =20k, from(2), r pu v il v ol 0.1v cc 1.1v cc v il 1.13 0.33 0.33 0.4 0.13 r s 2010 3 1.67 k r pu +r s (v cc v ol )r s + v ol +0.1v cc v il r s r pu microcontroller r s eeprom figure 51. i/o circuit diagram figure 52. input / output collision timing ack 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda r pu microcontroller r s eeprom i ol a bus line capacity cbus v ol v cc v il downloaded from: http:///
22 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 i 2 c bus input / output circuit input (scl0 to 3) input / output (sda0 to 3) input (wpb) notes on power on at power on, in ic internal circuit and set, v cc rises through unstable low voltage area, and ic inside is not c ompletely reset , and malfunction may occur. to prevent this, functions of por ci rcuit and lvcc circuit are equipped. to assure the action, observe the following conditions at power on. 1. set sda0 to 3 = 'h' and scl0 to 3 ='l' or 'h' 2. start power source so as to satisfy the recommended conditio ns of t r , t off , and vbot for operating por circuit. recommended conditions of t r , t off ,vbot t r t off vbot 10ms or below 10ms or longer 0.3v or below 100ms or below 10ms or longer 0.2v or below fi gure 55. input pin circuit diagram figure 56.input / output pin circuit diagram figure 57. input pin circuit diagram t off t r vbot 0 v cc figure 58. rise waveform diagram downloaded from: http:///
23 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 3. set sda0 to 3 and scl0 to 3 so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be observed, take t he following countermeasures. a) in the case when the above condition 1 cannot be observed. wh en sda0 to 3 becomes 'l' at power on. control scl0 to 3 and sda0 to 3 as shown below, to make scl0 to 3 and sda0 to 3, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(page 19 ). c) in the case when the above conditions 1 and 2 cannot be ob served. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and p revents wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. v cc noise countermeasures bypass capacitor when noise or surge gets in the power source line, mal function may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1 f) between ic v cc out and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board v cc out and gnd. cautions on use (1) reverse connection of power supply connecting the power supply in reverse polarity can damage the ic. take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the ic s power supply pin s. (2) power supply l ine s design the pcb layout pattern to provide low impedance supply lines. furthermore, connect a capacitor to ground at all power supply pins . consider the effect of temperature and aging on the capacita nce value when using electrolytic capacitors. (3) ground voltage ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. (4) ground wiring pattern when using both small-signal and large-current ground tra ces, the two ground traces should be routed separately but connected to a single ground at the reference point of the a pplication board to avoid fluctuations in the small-sign al ground caused by large currents. als o ensure that the ground traces of external components do not cause variations on the ground voltage. the ground lines must be as short a nd thick as possible to reduce line impedance. (5) th ermal consideration should by any chance the power dissipation rating be exc eeded the rise in temperature of the chip may result in deterioration of the properties of the chip. in case of exceedi ng this absolute maximum rating, increase the board size and copper area to prevent exceeding the pd rating. (6) recommended operating conditions these conditions represent a range within which the expe cted characteristics of the ic can be approximately obtaine d . the electrical characteristics are guaranteed under the condi tions of each parameter. t low t su :dat t dh after vcc becomes stable scl v cc sda after vcc becomes stable t su :dat figure 59. when scl0 to 3= 'h ' and sda0 to 3= 'l' figure 60. when s cl 0 to 3='l ' and sda0 to 3='l' downloaded from: http:///
24 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 (7) inrush current when power is first supplied to the ic, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence an d delays, especially if the ic has more than one power supply. therefore, give special consideration to power coup ling capacitance, power wiring, width of ground wiring, a nd routing of connections. (8) operation under strong electromagnetic field operating the ic in the presence of a strong electromagnetic field m ay cause the ic to malfunction. (9) testing on application boards when testing the ic on an application board, connecting a capacitor directly to a low-impedance output pin may subject the ic to stress. always discharge capacitor s completely after each process or step. the ics power su pply should always be turned off completely before connectin g or removing it from the test setup during the inspection process. to prevent damage from static discharge, ground the ic during assembly and use similar precautions during transport and storage. (10) inter-pin short and mounting errors ensure that the direction and position are correct when mountin g the ic on the pcb. incorrect mounting may result in damaging the ic. avoid nearby pins being shorted to each other especially to ground, power supply and output pin . inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) a nd unintentional solder bridge deposited in between pins during as sembly to name a few. (11) unused input pins input pins of an ic are often connected to the gate of a mos tra nsistor. the gate has extremely high impedance and extremely low capacitance. if left unconnected, the electric field from the outside can easily charge it. the small c harge acquired in this way is enough to produce a significan t effect on the conduction through the transistor and cause unexpected operation of the ic. so unless otherwise specifie d, unused input pins should be connected to the power supply or ground line. (12) regarding the input pin of the ic in the construction of this ic, p-n junctions are inevitably formed creating parasitic diodes or transistors. the operatio n of these parasitic elements can result in mutual interferen ce among circuits, operational faults, or physical damag e. therefore, conditions which caus e these parasitic elements to operate, such as applying a voltage to an input pin lower than the ground voltage should be avoided. furthermore, do not apply a voltage to the input pins when no power supply voltage is applied to the ic. even if the power suppl y voltage is applied, make sure that the input pin s have voltages within the values specified in the electrical characte ristics of this ic. downloaded from: http:///
25 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 ordering information b u 9 8 8 3 f v - w e 2 part number package fv: ssop-b16 packaging and forming specification e2 : embossed tape and reel physical dimension tape and reel information marking diagram ssop-b16 (top view) 9883 part number marking lot number 1pin mark ssop-b16 (bu9883fv- w) downloaded from: http:///
26 / 26 BU9883FV-W ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 17.aug.2015 rev.002 tsz02201-0r2r0g100420-1-2 revision history date revision changes 30.aug.2012 001 new release 17 .aug.2015 00 2 error in writing correction of the japanese sentence changed operational note downloaded from: http:///
datasheet d a t a s h e e t notice-pga-e rev.001 ? 2015 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (specific applications), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hms products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class ? class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohms products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. if the flow sol dering method is preferred on a surface-mount products, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
datasheet d a t a s h e e t notice-pga-e rev.001 ? 2015 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own indepen dent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohms internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since concerned goods might be fallen under listed items of export control prescribed by foreign exchange and foreign trade act, please consult with rohm in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. rohm shall not have any obligations where the claims, actions or demands arising from the co mbination of the products with other articles such as components, circuits, systems or external equipment (including software). 3. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the products or the informati on contained in this document. pr ovided, however, that rohm will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the produc ts, subject to the terms and conditions herein. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice C we rev.001 ? 201 5 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

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